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? 2010 semtech corporation december 16 , 2010 description v in : 3v to 5.5v v out : 0.75v to 95% x v in i out : up to 3a low r ds(on) switches up to 96% peak efciency enable high threshold: 1v compatible with low voltage logic high output accuracy small ceramic capacitors power good pin (open-drain) patented adaptive on-time control: excellent transient response programmable pseudo-fxed frequency fault protection features: cycle-by-cycle current limit short circuit protection over and under output voltage protection over-temperature internal soft start smart power save ultra-small lead-free 3x3mm, 10-pin mlpd package fully weee and rohs compliant ? ? ? ? ? ? ? ? ? ? ? ? ? ? applications networking equipment, embedded systems medical equipment, ofce automation instrumentation, portable systems consumer devices (dtv, set-top box, ... ) 5v pol converters ? ? ? ? ? the sc173a is an integrated, synchronous 3a ecospeed tm step-down regulator, which incorporates semtechs advanced, patented adaptive on-time archi - tecture to achieve best-in-class performance in dynamic point-of-load applications. the input voltage range is 3v to 5.5v with a programmable output voltage from 0.75v up to 95% x v in . the device features low-r ds(on) internal switches and automatic power save for high efciency across the output load range. adaptive on-time control provides programmable pseu - do-fxed frequency operation and excellent transient performance. the switching frequency can be set from 200khz to 1mhz - allowing the designer to reduce exter - nal lc fltering and minimize light load (standby) losses. additional features include cycle-by-cycle current limit, soft start, input uvlo and output ov protection, and over temperature protection. the open-drain pgood pin provides output status. standby current is less than 10 a when disabled. the device is available in a low profle, thermally en - hanced mlpd-3x3mm 10-pin package. features sc 173 a 3 to 5 . 5 v vin en pgnd enable agnd lx vdd power good fb pgood bst ton vout = 0 . 75 v to 95 % vin 3a ecospeed tm synchronous step-down regulator with automatic power save sc173a power management 1 typical application circuit
? 2010 semtech corporation pin confguration ordering information marking information agnd ton bst vin lx pgnd pgood vdd en fb device top mark package (2) sc173amltrt (1) 173a mlpd-10 3x3 SC173AEVB evaluation board notes: 1) available in tape and reel packaging only. a reel contains 3000 devices. 2) available in lead-free packaging only. weee compliant and halogen free. this component and all homogenous sub-components are rohs compliant. ja = 40c/w. 10 pin mlpd 173 a yyww xxxx top marking yyww = date code ( example : 0952 ) xxxx = semtech lot number ( example : 3901 ) 2 sc173a
? 2010 semtech corporation recommended operating conditions absolute maximum ratings thermal information lx to gnd (3) - 0.3(dc) to +6.0v(dc) max vin to pgnd, en to agnd -0.3 to +6.0v bst to lx -0.3 to +6.0v bst to pgnd -0.3 to +12v vdd to agnd, vout to agnd - 0.3v to +6.0v fb, pgood, ton -0.3 to vdd + 0.3v agnd to pgnd -0.3 to +0.3v peak ir refow temperature . 260c esd protection level (2) 1kv supply input voltage 3v to 5.5v maximum continuous output current 3a storage temperature -60 to +150c maximum junction temperature 150c operating junction temperature -40 to +125c thermal resistance, junction to ambient (1) 40 c/w exceeding the above specifcations may result in permanent damage to the device or device malfunction. operation outside of the parameters specifed in the electrical characteristics section is not recommended. electrical characteristics unless specifed: v in =5v, t a =+25c for typ, -40c to +85c for min and max, t j < 125c parameter symbol conditions min typ max units input supplies vin, vdd input voltage 3 5.5 v vdd uvlo threshold rising uvlo v th 2.75 2.85 2.98 v vdd uvlo hysteresis 100 200 mv vin, vdd supply current en= 0v 5 15 a i out =0a (1) 500 controller fb on-time threshold 0.7425 0.75 0.7575 v frequency programming range see r ton calculation 200 1000 khz fb input bias current fb=vdd or 0v -1 +1 a timing on-time in continuous conduction v in =5v, v out =3v, r ton =200k? 2.7 3 3.3 s minimum on-time (1) 80 ns minimum of-time (1) 250 ns notes- (1) calculated from package in still air, mounted to 3 x 4.5, 4 layer fr4 pcb with the rmal vias under the exposed pad per jesd51 standards. (2) tested according to jedec standard jesd22-a114-b (3) due to parasitic board inductance, the transient lx pin voltage at the point of measurement may appear larger than that which exists on silicon. the device is designed to tolerate the short duration transient voltages that will appear on the lx pin due to the deadtime diode conduction, for inductor currents up to the current limit setting of the device. see application section for details. 3 sc173a
? 2010 semtech corporation electrical characteristics (continued) parameter symbol conditions min typ max units power good power good threshold power good signal threshold high 116 120 124 %v out power good signal threshold low 86 90 93 pgood delay time (1) vdd=3v 1 ms vdd=5v 2 noise immunity delay time 5 s leakage 1 a power good on-resistance 10 20 ? fault protection output under-voltage fault fb with respect to ref, 8 consecutive clocks -30 -25 -20 % output over-voltage fault fb with respect to ref +16 +20 +24 % smart powersave protection threshold fb with respect to ref +7 +10 +13 % ov, uv fault noise immunity delay 5 s over-temperature shutdown ot latched 150 c enable output enabled 1 v output disabled 0.4 v en input bias current en = vdd or 0v 0.5 8.0 a enable pin floating voltage en foating 39 41 44 %v dd unless specifed: v in =5v, t a =+25c for typ, -40c to +85c for min and max, t j < 125c 4 sc173a
? 2010 semtech corporation electrical characteristics (continued) note: (1) typical value from evb, not ate tested. parameter symbol conditions min typ max units gate drivers bst switch on resistance 25 45 ? internal power mosfets current limit valley current limit, vdd=5v 3.5 a valley current limit, vdd=3v 3 3.5 lx leakage current vin=5.5v, lx=0v, high side 1 10 a switch resistance high side 60 85 m? low side 50 75 non-overlap time (1) 30 ns unless specifed: v in =5v, t a =+25c for typ, -40c to +85c for min and max, t j < 125c 5 sc173a
? 2010 semtech corporation pin descriptions (mlpd-10) pin # pin name pin function 1 bst bootstrap pin. a capacitor is connected between bst to lx to develop the foating voltage for the high-side gate drive. 2 vin power input supply voltage. 3 lx switching (phase) node. 4 pgnd power ground. 5 pgood open-drain power good indicator. high impedance indicates power is good. an e xternal pull-up resistor is required. 6 fb feedback input for switching regulator. connect to an external resistor divider from the output to program the output voltage. 7 en enable input for the switching regulator. pull en above 1v or foat it to enable the part with auto - matic power save mode enabled. connect en to agnd to disable the switching regulator. 8 ton on-time set input. set the on-time by a series resistor to agnd . 9 agnd analog ground. 10 vdd input power for internal control circuit. needs at least 2.2 m f decoupling capacitor from this pin to agnd. pad thermal pad for heatsinking purposes. connect to ground plane using multiple vias. not con - nected internally. 6 sc173a
? 2010 semtech corporation block diagram en pgood vdd agnd fb ton pgnd vdd lx vin bst gate drive control zero - cross valley current limit r control on - time generator reference soft start vdd 8 6 9 10 7 5 1 2 3 4 7 sc173a
? 2010 semtech corporation efficienc y vs output current 75.0 80.0 85.0 90.0 95.0 100.0 0.00 0.75 1.50 2.25 3.00 output current ( a) efficiency (%) vin=5v, vo=3.3v, l out : ds84lc-b1015as-2r2n c out =22 m fx2 r ton = 80.6kohm efficienc y vs output current 55.0 60.0 65.0 70.0 75.0 80.0 85.0 90.0 95.0 0.01 0.76 1.51 2.26 3.01 output current ( a) efficiency (%) vin=5v, vo=1.2v, l out : ds84lc-b1015as-2r2n c out =22 m f r ton = 54.9kohm efficienc y vs output current 65.0 70.0 75.0 80.0 85.0 90.0 95.0 0.00 0.60 1.20 1.80 2.40 3.00 output current ( a) efficiency (%) vo=1.2v, r ton = 54.9kohm l out :ds84lc-b1015as-2r2n c out :22 m f red:vin = 3.5v green: vin = 4.0v blue: vin = 5.0v output voltage vs output current 3.270 3.279 3.287 3.296 3.304 3.313 3.322 3.330 3.339 0.00 0.75 1.50 2.25 3.00 output current ( a) output voltage (v) vin=5v, vo=3.305v, l out : ds84lc-b1015as-2r2n c out =22 m fx2 r ton = 80.6kohm output voltage vs output current 1.210 1.212 1.214 1.216 1.218 0.00 0.60 1.20 1.80 2.40 3.00 output current ( a) output voltage (v) vin=5v, vo=1.212v, l out : ds84lc-b1015as-2r2n c out =22 m f r ton = 54.9kohm output voltage vs output current 1.201 1.204 1.206 1.209 1.211 1.214 1.216 0.00 0.75 1.50 2.25 3.00 output current ( a) output voltage (v) vo=1.212v, r ton = 54.9kohm l out : ds84lc-b1015as-2r2n c out :22 m f black: vin=5v red: vin=4v blue: vin=3.5v typical characteristics 8 sc173a
? 2010 semtech corporation typical characteristics fb voltage vs temperature 0.745 0.748 0.750 0.753 0.755 -40 -15 10 35 60 85 110 135 temperature (c) fb voltage (v) black:vdd=5.0v red: vdd=3.0v i bst leakage current vs temperature -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 -50 -25 0 25 50 75 100 125 temperature (c) i bst leakage current ( p a) v in =5v v bst =v in start up waveform ( v in =5v, v out =1.2v, i out =3a, channel 1: 500mv/div, channel 4: 1a/div, time: 1ms/div ) load transient test ( v in =5v, v out =1.2v, i out = 0a to 3a, l out =1.0 p h,c out =2x22 p f,channel 1: 50mv/div, channel 2:5v/div,channel 4:2a/div,time:20 p s/div) load transient test ( v in =5v, v out =1.2v, i out = 3a to 0a, l out =1.0 p h, c out =2x22 p f, channel 1: 50mv/div,channel 2:5v/div,channel 4:2a/div, time:20 p s/div) i vin input current in shutdown vs temperature 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -50 -25 0 25 50 75 100 125 temperature (c) i vin input current in shutdown ( p a) v in =5v blue: v lx =gnd black: v lx =v in 9 sc173a
? 2010 semtech corporation low side switch on-state resistance vs te mp erature 30 34 38 42 46 50 54 58 -40 -15 10 35 60 85 110 135 temperature (c) on-state resistance (m ? ) blue: vdd=3.0v black: vdd=5.0v high side switch on-state resistance vs te mperature 40 44 48 52 56 60 64 -40 -15 10 35 60 85 110 135 temperature (c) on-state resistance (m ? ) blue: vdd=3.0v black: vdd=5.0v typical characteristics 10 sc173a
? 2010 semtech corporation applications information sc173a synchronous buck converter the sc173a is a step down synchronous buck dc-dc regu - lator. the sc173a is capable of 3a operation at very high efciency in a tiny 3x3-10 pin package. the programma - ble operating frequency range of 200khz C 1mhz (con - tinuous conduction mode) enables the user to optimize the solution for minimum board space and optimum ef - fciency. the buck regulator employs pseudo-fxed frequency adaptive on-time control. this control scheme allows fast transient response thereby lowering the size of the power components used in the system. input voltage range the sc173a can operate with an input voltage ranging from 3v to 5.5v. psuedo-fxed frequency adaptive on-time control the pwm control method used by the sc173a is pseudo- fxed frequency, adaptive on-time, as shown in figure 1. the ripple voltage generated at the output capacitor esr is used as a pwm ramp signal. this ripple is used to trig - ger the on-time of the controller. the adaptive on-time is determined by an internal one- shot timer. when the one-shot is triggered by the out - put ripple, the device sends a single on-time pulse to the high-side mosfet. the pulse period is determined by v out and v in ; the period is proportional to output voltage and inversely proportional to input voltage. with this adaptive on-time arrangement, the device automatically anticipates the on-time needed to regulate v out for the present v in condition and at the selected frequency. the advantages of adaptive on-time control are: predictable operating frequency compared to other variable frequency methods. reduced component count by eliminating the error amplifer and compensation compo - nents. reduced component count by removing the need to sense and control inductor current. fast transient response the response time is controlled by a fast comparator instead of a typically slow error amplifer. reduced output capacitance due to fast tran - sient response one-shot timer and operating frequency the one-shot timer operates as shown in figure 2. the fb comparator output goes high when v fb is less than the internal 750mv reference. this feeds into the gate drive and turns on the high-side mosfet, and also starts the one-shot timer. the one-shot timer uses an internal comparator, timing capacitor, and a low pass flter (lpf) which regenerates v out from lx. one comparator input is connected to the fltered lx voltage, the other input is connected to the capacitor. when the on-time begins, the internal capacitor charges from zero volts through a current which is proportional to v in . when the capacitor voltage reaches v out , the on-time is completed and the high-side mosfet turns of. this method automatically produces an on-time that is proportional to v out and inversely proportional to v in . under steady-state operation conditions, the switching frequency can be determined from the on-time by the following equation. ? ? ? ? ? q 1 q 2 l c out v in esr + v lx fb c in v out t on v lx fb threshold v fb figure 1 pwm control method, v out ripple in on out sw v t v f = 11 sc173a
? 2010 semtech corporation + - hi - side and lo - side gate drivers pwm on - shot timing generator time = k x v out / v in v out v in fb ref s r q q 1 q 2 l c out v in esr + v out v lx fb lpf r ton the sc173a uses an external resistor to set the on-time which indirectly sets the frequency. the on-time can be programmed to provide operating frequency from 200khz to 1mhz using a resistor between the ton pin and ground. the resistor value is selected by the fol - lowing equation. v out voltage selection the switcher output voltage is regulated by comparing v out as seen through a resistor divider at the fb pin to the internal 750mv reference voltage, see figure 3. figure 3 output voltage selection note that this control method regulates the valley of the output ripple voltage, not the dc value. the dc output voltage v out is ofset by the output ripple according to the following equation. figure 2 on-time generation sw ton f 25pf 1 r ? = r 1 v out to fb pin r 2 2 v r r 1 0.75v v ripple 2 1 out + ? ? ? ? ? ? ? ? + ? = enable input the en input is used to enable or disable the switching regulator. when en is low (grounded), the switching reg - ulator is of and in its lowest power state. when of, the output power switches are tri-stated. when en is pulled high (above 1v), or permitted to foat, the switching regulator turns on with automatic power save enabled. smart power save protection active loads may leak current from a higher voltage into the switcher output. under light load conditions with power save enabled, this can force v out to slowly rise and reach the over-voltage threshold, resulting in a hard shutdown. smart power save prevents this condi - tion. when the fb voltage exceeds 10% above nominal (exceeds 825mv), the device immediately disables powe save, and dl drives high to turn on the low-side mosfet. this draws current from v out through the inductor and causes v out to fall. when v fb drops back to the 750mv trip point, a normal t on switching cycle begins. this method prevents a hard ovp shutdown and also cycles energy from v out back to v in . figure 4 shows typical waveforms for the smart power save feature. figure 4 smart power save current limit protection the device features fxed current limiting, which is ac - complished by using the r ds(on) of the lower mosfet for current sensing. while the low-side mosfet is on, the applications information (continued) fb threshold high - side drive ( dh ) low - side drive ( dl ) v out drifts up to due to leakage current flowing into c out dh and dl off dl turns on when smart psave threshold is reached smart power save threshold ( 825 mv ) dl turns off when fb threshold is reached single dh on - time pulse after dl turn - off v out discharges via inductor and low - side mosfet normal dl pulse after dh on - time pulse normal v out ripple 12 sc173a
? 2010 semtech corporation inductor current fows through it and creates a voltage across the r ds(on) . during this time, the voltage across the mosfet is negative with respect to ground. during this time, if this mosfet voltage drop exceeds the internal reference voltage, the current limit will activate. the cur - rent limit then keeps the low-side mosfet on and will not allow another high side on-time, until the current in the low-side mosfet reduces enough to drop below the internal reference voltage once more. this method regu - lates the inductor valley current at the level shown by i lim in figure 5. figure 5 valley current limit setting the valley current limit to a value of i lim results in a peak inductor current of ilim plus the peak-to-peak ripple current. in this situation, the average (load) current through the inductor will be i lim plus one half the peak- to-peak ripple current. soft start of pwm regulator soft start is achieved in the pwm regulator by using an internal voltage ramp as the reference for the fb comparator. the voltage ramp is generated using an internal charge pump which drives the reference from zero to 750mv in ~1.8mv increments, using an internal ~500khz oscillator. when the ramp voltage reaches 750mv, the ramp is ignored and the fb comparator switches over to a fxed 750mv threshold. during soft start the output voltage tracks the internal ramp, which limits the start-up inrush current and provides a controlled soft start profle for a wide range of applications. typical soft start ramp time is 0.85ms. during soft start the regulator turns off the low-side mosfet on any cycle if the inductor current falls to zero. this prevents negative inductor current, allowing the device to start into a pre-biased output. power good output the power good (pgood) output is an open-drain output which requires a pull-up resistor. when the output volt - age is 10% below the nominal voltage, pgood is pulled low. it is held low until the output voltage returns to the nominal voltage. pgood is held low during soft start and activated approximately 1ms after v out reaches regula - tion. the total pgood delay is typically 2ms. pgood will transition low if the v fb pin exceeds +20% of nominal, which is also the over-voltage shutdown thresh - old (900mv). pgood also pulls low if the en pin is low when vdd is present. output over-voltage protection over-voltage protection (ovp) becomes active as soon as the device is enabled. the threshold is set at 750mv + 20% (900mv). when v fb exceeds the ovp threshold, dl latches high and the low-side mosfet is turned on. dl remains high and the controller remains of, until the en input is toggled or vdd is cycled. there is a 5s delay built into the ovp detector to prevent false transitions. pgood is also low after an ovp event. output under-voltage protection when v fb falls to 75% of its nominal voltage (falls to 562.5mv) for eight consecutive clock cycles, the switcher is shut of and the dh and dl drives are pulled low to turn of the mosfets. the controller stays of until en is tog - gled or vdd is cycled. vdd uvlo, and por under-voltage lock-out (uvlo) circuitry inhibits switch - ing and tri-states the power fets until vdd rises above 2.9v. an internal power-on reset (por) occurs when vdd exceeds 2.9v, which resets the fault latch and soft start counter to begin the soft start cycle. the sc173a then begins a soft start cycle. the pwm will shut of if vdd falls below 2.7v. time i peak i load i lim i n d u c t o r c u r r e n t 13 sc173a
? 2010 semtech corporation design procedure when designing a switch mode supply the input voltage range, load current, switching frequency, and inductor ripple current must be specifed. the maximum input voltage (v inmax ) is the highest speci - fed input voltage. the minimum input voltage ( v inmin ) is determined by the lowest input voltage after evaluating the voltage drops due to connectors, fuses, switches, and pcb traces. the following parameters defne the design. nominal output voltage (v out ) static or dc output tolerance transient response maximum load current (i out ) there are two values of load current to evaluate con - tinuous load current and peak load current. continuous load current relates to thermal stresses which drive the selection of the inductor and input capacitors. peak load current determines instantaneous component stresses and fltering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. the following values are used in this design. v in = 5v + 10% v out = 1.0v + 4% f sw = 800khz load = 3a maximum frequency selection selection of the switching frequency requires making a trade-of between the size and cost of the external flter components (inductor and output capacitor) and the power conversion efciency. the desired switching frequency is 800khz which results from using components selected for optimum size and cost . a resistor (r ton ) is used to program the on-time (indirectly ? ? ? ? ? ? ? ? applications information (continued) setting the frequency) using the following equation. calculating r ton results in the following solution. r ton =50k w, we use r ton =49.9k w in real application. inductor selection in order to determine the inductance, the ripple cur - rent must frst be defned. low inductor values result in smaller size but create higher ripple current which can reduce efciency. higher inductor values will reduce the ripple current/voltage and for a given dc resistance are more efcient. however, larger inductance translates di - rectly into larger packages and higher cost. cost, size, output ripple, and efciency are all used in the selection process. the ripple current will also set the boundary for power save operation. the switching will typically enter power save mode when the load current decreases to 1/2 of the ripple current. for example, if ripple current is 3a then power save operation will typically start for loads less than 1.5a. if ripple current is set at 40% of maximum load current, then power save will start for loads less than 20% of maximum current. the inductor value is typically selected to provide a rip - ple current that is between 25% to 50% of the maximum load current. this provides an optimal trade-of between cost, efciency, and transient performance. during the dh on-time, voltage across the inductor is (v in - v out ). the equation for determining inductance is shown next. sw ton f 25pf 1 r ? = ripple on out in i t ) v - (v l = sw inmax out on f v v t ? = 14 sc173a
? 2010 semtech corporation example in this example, the inductor ripple current is set equal to 30% of the maximum load current. therefore ripple current will be 30% x 3a or 0.9a. to fnd the minimum inductance needed, use the v in and t on values that cor - respond to v inmax . a larger value of 2h is selected. this will decrease the maximum i ripple to 0.511a. note that the inductor must be rated for the maximum dc load current plus 1/2 of the ripple current. the ripple current under minimum v in conditions is also checked using the following equations. capacitor selection the output capacitors are chosen based on required esr and capacitance. the maximum esr requirement is con - trolled by the output ripple requirement and the dc tol - erance. the output voltage has a dc value that is equal to the valley of the output ripple plus 1/2 of the peak- to-peak ripple. change in the output ripple voltage will lead to a change in dc voltage at the output. the design goal is for the output voltage regulation to be 4% under static conditions. the internal 750mv refer - ence tolerance is 1%. assuming a 1% tolerance from the fb resistor divider, this allows 2% tolerance due to v out ripple. since this 2% error comes from 1/2 of the ripple voltage, the allowable ripple is 4%, or 40mv for a 1v out - put. applications information (continued) the maximum ripple current of 0.511a creates a ripple voltage across the esr. the maximum esr value allowed is shown by the following equations. 0.51a mv 40 i v esr ripplemax ripple max = = esr max = 78.3 m? the output capacitance is chosen to meet transient re - quirements. a worst-case load release, from maximum load to no load at the exact moment when inductor cur - rent is at the peak, determines the required capacitance. if the load release is instantaneous (load changes from maximum to zero in < 1s), the output capacitor must absorb all the inductors stored energy. this will cause a peak voltage on the capacitor according to the following equation. assuming a peak voltage v peak of 1.050v (50mv rise upon load release), and a 3a load release, the required capaci - tance is shown by the next equation. if the load release is relatively slow, the output capacitance can be reduced. at heavy loads during normal switching, when the fb pin is above the 750mv reference, the dl output is high and the low-side mosfet is on. during this time, the voltage across the inductor is approximately -v out . this causes a down-slope or falling di/dt in the inductor. if the load di/dt is not much faster than the -di/dt in the inductor, then the inductor current will tend to track the falling load current. this will reduce the excess inductive energy that must be absorbed by the output capacitor, therefore a smaller capacitance can be used. the following can be used to calculate the needed ca - pacitance for a given di load /dt. peak inductor current is shown by the next equation. h 14 . 1 0.9a 227ns 1v) - (5.5v l m = ? = 227ns khz 800 5.5v 1v t on_vinmax = ? = 0.485a h 2 277ns 1v) - (4.5v i min ripple_vin = m = l t ) v - (v i on out in ripple = 277ns 800khz 4.5v 1v t on_vinmin = = 2 out 2 peak 2 ripplemax out min ) (v - ) (v ) i 2 1 (i l cout + = f 207 (1.0v) - (1.05v) 0.511a) 2 1 (3a h 2 cout 2 2 2 min m = + m = 15 sc173a
? 2010 semtech corporation applications information (continued) rate of change of load current is i max = maximum load release = 3a note that c out is much smaller in this example, 50f com - pared to 207f based upon a worst-case load release. to meet the two design criteria of minimum 50f and maxi - mum 78m ? esr , select two capacitors rated at 33f and 15m ? esr or less . it is recommended that an additional small capacitor be placed in parallel with c out in order to flter high frequen - cy switching noise. stability considerations unstable operation is possible with adaptive on-time controllers, and usually takes the form of double-pulsing or esr loop instability. double-pulsing occurs due to switching noise seen at the fb input or because the fb ripple voltage is too low. this causes the fb comparator to trigger prematurely af - ter the minimum of-time has expired. in extreme cases the noise can cause three or more successive on-times. double-pulsing will result in higher ripple voltage at the output, but in most applications it will not afect opera - tion. this form of instability can usually be avoided by providing the fb pin with a smooth, clean ripple signal that is at least 10mvp-p, which may dictate the need to increase the esr of the output capacitors. it is also im - perative to provide a proper pcb layout as discussed in the layout guidelines section. another way to eliminate doubling-pulsing is to add a small (~ 10pf) capacitor across the upper feedback resis - tor, as shown in figure 6. this capacitor should be left unpopulated unless it can be confrmed that double- pulsing exists. adding the c top capacitor will couple more ripple into fb to help eliminate the problem. an optional connection on the pcb should be available for this capacitor. v out to fb pin r 2 r 1 c top figure 6 capacitor coupling to fb pin esr loop instability is caused by insufcient esr. the details of this stability issue are discussed in the esr re - quirements section. the best method for checking sta - bility is to apply a zero-to-full load transient and observe the output voltage ripple envelope for overshoot and ringing. ringing for more than one cycle after the initial step is an indication that the esr should be increased. one simple way to solve this problem is to add trace re - sistance in the high current output path. a side efect of adding trace resistance is a decrease in load regulation. esr requirements a minimum esr is required for two reasons. one reason is to generate enough output ripple voltage to provide 10mvp-p at the fb pin (after the resistor divider) to avoid double-pulsing. the second reason is to prevent instability due to insuf - fcient esr. the on-time control regulates the valley of the output ripple voltage. this ripple voltage is the sum of the two voltages. one is the ripple generated by the esr, the other is the ripple due to capacitive charging s 1 0.6a dt di load m = 1v) - (1.05v 2 s 1 0.6a 3a - 1v 3.26a h 2 3.26a c out m m ? = f 50 c out m = 3.26a 0.511a 2 1 3a i lpk = + = ) v - v ( 2 dt di i - v i l i c out pk load max out lpk lpk out = 16 sc173a
? 2010 semtech corporation applications information (continued) and discharging during the switching cycle. for most ap - plications, the total output ripple voltage is dominated by the output capacitors, typically sp or poscap devices. for stability the esr zero of the output capacitor should be lower than approximately one-third the switching fre - quency. the formula for minimum esr is shown by the following equation. using ceramic output capacitors when applications use ceramic output capacitors, the esr is normally too small to meet the previously stated esr criteria. in these applications it is necessary to add a small signal injection network as shown in figure 7. in this network r l and c l flter the lx switching waveform to generate an in-phase ripple voltage comparable to the ripple seen on higher esr capacitors. c c is a coupling ca - pacitor used to ac couple the generated ripple onto the fb pin. capacitor c ff is required for min c out applications. this capacitor introduces a lead/lag into the control with the maximum phase placed at 1/2 f sw for added stability. q 1 q 2 v lx l r l c l c c r 1 r 2 c out v in c ff figure 7 signal injection circuit the values of r l , c l , c c and c ff are dependent on the con - ditions of the specifc application such as v in , v out , f sw and i out . for switching frequencies ranging from 600khz to 800khz, calculations plus experimental test results show that the following combination of r l =2.5k w , c l =10nf, c c =68pf and c ff =39pf can be used for many output volt - ages and loads. output voltage dropout the output voltage adjustable range for continuous- conduction operation is limited by the fxed 320ns (typi - cal) minimum of-time. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and of times. the duty-factor limitation is shown by the next equation. ) max ( off ) min ( on ) min ( on t t t duty the inductor resistance and mosfet on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. system dc accuracy v out controller three factors afect v out accuracy: the trip point of the fb error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. the error comparator ofset is trimmed so that under static condi - tions it trips when the feedback pin is 750mv, + 1%. the on-time pulse from the sc173a in the design ex - ample is calculated to give a pseudo-fxed frequency of 800khz. some frequency variation with line and load is expected. this variation changes the output ripple volt - age. because adaptive on-time converters regulate to the valley of the output ripple, ? of the output ripple ap - pears as a dc regulation error. for example, if the output ripple is 50mv with v in = 5 volts, then the measured dc output will be 25mv above the comparator trip point. if the ripple increases to 30mv with v in = 5.5v, then the measured dc output will be 15mv above the comparator trip. the best way to minimize this efect is to minimize the output ripple. to compensate for valley regulation, it may be desirable to use passive droop. take the feedback directly from the output side of the inductor and place a small amount of trace resistance between the inductor and output ca - pacitor. this trace resistance should be optimized so that at full load the output droops to near the lower regula - tion limit. passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced as seen at the load. sw out min f c 2 3 esr = 17 sc173a
? 2010 semtech corporation applications information (continued) the use of 1% feedback resistors may result in up to an additional 1% error. if tighter dc accuracy is required, re - sistors with lower tolerances should be used. the output inductor value may change with current. this will change the output ripple and therefore will have a minor efect on the dc output voltage. the output esr also afects the output ripple and thus has a minor efect on the dc output voltage. switching frequency variation the switching frequency will vary depending on line and load conditions. the line variations are a result of fxed propagation delays in the on-time one-shot, as well as unavoidable delays in the power fet switching. as v in increases, these factors make the actual dh on-time slightly longer than the ideal on-time. the net efect is that frequency tends to fall slightly with increasing input voltage. the switching frequency also varies with load current as a result of the power losses in the mosfets and the inductor. for a conventional pwm constant-frequency converter, as load increases the duty cycle also increases slightly to compensate for ir and switching losses in the mosfets and inductor. a adaptive on-time converter must also compensate for the same losses by increasing the efective duty cycle (more time is spent drawing en - ergy from v in as losses increase). the on-time is essential - ly constant for a given v out and v in combination, to ofset the losses the of-time will tend to reduce slightly as load increases. the net efect is that switching frequency in - creases slightly with increasing load. switching node voltage spike due to parasitic board inductance, the transient lx pin voltage at the point of measurement may appear larger than that which exists on silicon. with an input multilay - er ceramic capacitor of 10uf placed less than 3mm away from the pvin pin, the device is designed and guaranteed to tolerate the short transient voltages, of maximum 20ns duration, that will appear on the lx pin due to the deadtime diode conduction, as long as the transient volt - age on pvin is less than 6.0v. the time duration of the transient lx pin voltage is measured on the voltage por - tion which is either over 6.0v for positive voltage spike or under -1v for negative voltage spike. the lx voltage is measured from the lx pin to the pgnd pin by using a probing loop which is as short as possible to minimize or eliminate the switching noise pick up. 18 sc173a
? 2010 semtech corporation layout guideline since the sc173a has integrated switches, special con - sideration should be given to board layout. let us use the schematic shown above as an example. the board level layout is illustrated in the following four layers. as shown on the top layer layout, u1 is the switching regulator sc173a. c1 and c11 serve as the decoupling capacitor for the buck converter power train. c11, with a value between 1nf and 10nf, is the high frequency flter - ing capacitor. it is recommended to put c1 and c11 as close as possible to the sc173a to get the best decou - pling performance, with c11 closest. c1, with a value of 10uf, should be placed no more than 3mm away from the vin pin. l1 is the output fltering inductor. c2, c3 and c4 are the output fltering capacitors. c5 is the boostrap capacitor. pin 10 (vdd) is the input bias power for the internal circuits. it is recommended to get the power from vin through an rc fltering network consisted of r1, c6 and c10. the value of r1 can be between 3.01 w and 10 w and the capacitance of c10 should be above 1 m f. c6, with a value of 1nf, is the high frequency fltering ca - pacitor. the locations of c6 and c10 should be as close as possible to pins 9 and 10, with c6 closest, to get the best possible fltering result. r2 is the on-time programming resistor. r2 should be located as close as possible to pin 8 and it should return to analog ground. pull en high (above 1v) or permit it to foat to enable the part with automatic power save enabled. connect en to agnd to disable the switching regulator. since there are two integrated mosfets inside the sc173a that will dissipate a lot of power, to help spread the heat out of the ic more efciently, there is a thermal pad underneath the sc173a serving as a heat sink. to enlarge the heat sinking area, a large copper plane un - der the thermal pad as shown on the top layer is recom - mended. on inner layer 2, a large analog ground plane (agnd) on the right hand side is connected to the thermal pad un - derneath the sc173a using vias. thus the heat generated inside the sc173a can be spread through the vias to the 1 2 3 4 5 6 7 9 10 0 c 5 c 6 0 r 6 c 8 0 bst vin lx pgnd en ton agnd vdd pgood fb p a d c 3 l 1 c 2 r 3 r 2 0 r 1 c 1 r 4 r 7 c 9 0 c 4 c 7 enable v in + v in - v o + v o - u 1 sc 173 a c 10 c 11 8 schematic for layout illustration 19 sc173a
? 2010 semtech corporation inner layers to expand the heat sinking area. on the bottom layer, the resistor network composed of r3 and r4 determines the output voltage. c7 is the feed forward capacitor which helps to stabilize the circuit. r6 in series with c9 is connected to the lx pin (through the via) to the power ground. c8 is the coupling capacitor which injects the ramp signal generated on c9 to the fb pin of the sc173a. r7 is the pull up resistor for the pgood pin. 20 sc173a
? 2010 semtech corporation pgnd v o + v o agnd agnd c 11 l 1 c 3 c 4 c 5 c 6 r 1 r 2 u 1 c 2 v o + agnd v o 1 2 3 4 5 6 7 8 9 10 pgnd lx vin + inner layer 1 top layer v in + en / psv c 10 c 1 v in v in 21 sc173a
? 2010 semtech corporation v o + agnd 1 2 3 4 5 6 7 8 9 10 pgnd lx vin + v in v o + agnd v o r 3 r 4 c 7 c 8 r 6 r 7 1 2 3 4 5 6 7 8 9 10 bottom layer inner layer 2 lx pgnd v in v o c 9 22 sc173a
? 2010 semtech corporation typical application circuits c 18 68 pf r 2 15 k c 4 1 uf / 6 . 3 v vout + c 19 10 n r 6 9 . 09 k r 5 2 . 5 k r 3 54 . 9 k fb c 5 10 uf / 6 . 3 v bst vin lx pgnd en / psv ton agnd vdd pgood fb c 1 10 uf / 6 . 3 v vout - r 4 100 k c 10 38 p vin - c 6 22 uf / 6 . 3 v l 1 2 . 0 uh r 1 5 . 11 ohm vin + sc 173 a enable fb c 101 0 . 1 uf / 6 . 3 v c 501 0 . 1 uf / 6 . 3 v application circuit: buck converter with 1.2v out and 0 to 3a load current (vin=5v) c 18 68 pf r 2 15 k c 4 1 uf / 6 . 3 v vout + c 19 10 n r 6 51 . 1 k r 5 4 . 32 k r 3 80 . 6 k c 5 10 uf / 6 . 3 v bst vin lx pgnd en / psv ton agnd vdd pgood fb c 1 10 uf / 6 . 3 v vout - r 4 100 k c 10 38 p vin - c 6 22 uf / 6 . 3 v l 1 2 . 0 uh r 1 5 . 11 ohm vin + sc 173 a fb enable fb 0 . 1 uf / 6 . 3 v c 101 0 . 1 uf / 6 . 3 v c 501 22 uf / 6 . 3 v c 2 application circuit: buck converter with 3.3v out and 0 to 3a load current (vin=5v) 23 sc173a
? 2010 semtech corporation outline drawing - mlpd-10 3x3 notes: controlling dimensions are in millimeters (angles in degrees). coplanarity applies to the exposed pad as well as terminals. 2. 1. .003 .008 10 .010 - .000 .031 (.008) 0.08 0.25 10 .012 0.20 .039 - .002 - 0.00 0.80 0.30 - 0.05 1.00 (0.20) .004 0.10 0.50 bsc .020 bsc 0.45 .018 .022 .020 0.50 0.55 aaa c seating plane a bbb c a b b e c .114 .118 .122 2.90 3.00 3.10 - - - - (laser mark) indicator pin 1 1 n 2 min aaa bbb b e l n d e1 a1 a2 a dim millimeters nom dimensions max nom inches min max .057 .059 .061 1.45 1.50 1.55 d e a1 a2 d/2 d1 .087 .089 .091 2.20 2.25 2.30 e .114 .118 .122 2.90 3.00 3.10 a d1 e1 e/2 bxn lxn 24 sc173a
? 2010 semtech corporation land pattern - mlpd-10 3x3 g y k h .087 .055 2.20 1.40 .146 .020 .012 .031 3.70 0.30 0.80 0.50 (.114) .083 2.10 (2.90) this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 2. thermal vias in the land pattern of the exposed pad shall be connected to a system ground plane. functional performance of the device. failure to do so may compromise the thermal and/or 3. 1. inches dimensions g k h x y p z c dim millimeters controlling dimensions are in millimeters (angles in degrees). x p z (c) controlling dimensions are in millimeters (angles in degrees). dimensions inches c (.112) failure to do so may compromise the thermal and/or functional performance of the device. shall be connected to a system ground plane. thermal vias in the land pattern of the exposed pad this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 3. 2. 1. x z y k p h g .012 .033 .146 .079 .020 .059 .089 dim (2.85) 0.30 0.85 3.70 2.00 0.50 1.50 2.25 millimeters x p g y z (c) h k 25 sc173a
? 2010 semtech corporation ? semtech 2010 all rights reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specifed maximum ratings or operation outside the specifed range. semtech products are not designed, intended, authorized or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. inclusion of semtech products in such ap - plications is understood to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized application, the customer shall indemnify and hold semtech and its ofcers, em - ployees, subsidiaries, afliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. contact information semtech corporation power mangement products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 www.semtech.com 26 sc173a

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